Communication switching system having separate register subsystem and stored program processor each having its own memory,and data transfer by processor access to the register memory

ABSTRACT

The order set of the stored program processor includes two special instructions to provide direct access to the register subsystem memory instead of the main processor memory, one to read a word from the register memory and one to write data in a word thereof, in each case at the effective address in the register memory designated by the instruction. There may be two separate register subsystems, and one bit of the address selects the subsystem. Both the processor and each of the register subsystems is duplicated, and either copy of the processor may communicate with either copy of the selected register subsystem. There are also command pulse directives which may be sent from the processor to a selected register subsystem, and sense line and interrupt signal lines from each register subsystem to the processor.

United States Patent [191 Zelinski COMMUNICATION SWITCHING SYSTEM HAVINGSEPARATE REGISTER SUBSYSTEM AND STORED PROGRAM PROCESSOR EACH HAVING ITSOWN MEMORY, AND DATA TRANSFER BY [111 3,820,085 [4 June 25, 1974 6/l97lQuinn 340/l72.5 7/[973 Dufton 179/18 ES PROCESSDR ACCESS TO THE REGISTER57] ABSTRACT MEMORY The order set of the stored program processor in-[75] Inventor: Paul A. Zelinski, Elmhurst, Ill. eludes two specialinstructions to provide direct access [73] Assi GTE Automatic Electricto the register subsystem memory instead of the main g Laboratorieslncor rated processor memory, one to read a word from the register memoan one to write ata m a wor t ereo in Northlake in P0 d d I f' each caseat the efi'ective address in the register mem- [22] Filed: Apr. 6, 1973ory designated by the instruction. There may be two separate registersubsystems, and one bit of the ad- [211 App! 348315 dress selects thesubsystem. Both the processor and each of the register subsystems isduplicated, and ei- [52] US. Cl. 340/ 172.5, l79/l8 ES ther copy of theprocessor may communicate with ei- [5 l] Int. Cl. G05b 15/00, H04m 3/00ther copy of the selected register subsystem. There are [58] Field ofSearch 340/ 172.5; 179/18 ES also command pulse directives which may besent from the processor to a selected register subsystem, [56]References Cited and sense line and interrupt signal lines from eachreg- UN TE STATES T N ister subsystem to the processor. 3,408,628l0/l968 Brass ct al. 340/1725 3 Claims, 22 Drawing Figures 1 DATA Bus 09j Y REGISTER PCA -H ARlT i-i iid ETlC INSTRISCTION x! INXDZEX INXD3EX5363' ggggEE-H C O tRl T LOGIC UNIT REGISTER RE G l TER REG'STERREGISTER COUNTER L CPD oecooea EQ L REGIETER REGITER REGIgTER c n E gggl g? m? fifii F l Lgg AND BUSES L ADDRESS eus A8 I j DATA ADDRESS R52swam; CTP GENERATOR on CSL CTP TIM ING GENERATOR CPT CONTROL UNITCOMPUTER C ENTRAL PROCESSOR CCP PATENTEDJUHZS 19M 3; 820,085

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sum 05 0f 19 DATA BUS SOURCES'BIT Q LATCH RSI DATAQS-l Rs\ADso RS2 DATARSI DATA RS2 DATA 5-2 RS25- CCX CTP 540 FIG. 5

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sum 11 or 19 ARITHMETPC LOGIC UNIT ALU F l6. l2

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sum 12 ur 19 A REGSTER FIG /3 ggslsTeR I I TO E|VEN FF'S PAIHHHWEWM3.820.085

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1. In a communication switching system comprising common controlapparatus and a switching network with markers for control thereof, inwhich the common control apparatus comprises a register-sender subsystemand a stored program data processing unit; wherein the registersubsystem comprises a plurality of register junctors, a register memorywhich has junctor memory areas individual to the register junctors acommon logic unit, said common logic unit including a timing generatorwhich supplies cyclically recurring time slot signals, and time divisionmultiplex means effectively coupling the register junctors and theirindividual memory areas to the common logic during their time slots forreceiving, storing and other processing of call digit information, withthe address for reading and writing into the register memory derivedfrom the time slot signals, whereby the register subsystem access to theregister memory is on a sequential access basis; wherein the dataprocessing unit comprises a computer central processor and a mainmemory; in which the computer central processor comprises a plurality ofregisters including an instruction register and an accumulator register,bus means, control means, source gating means coupling outputs of theregisters and the output of a main memory to the bus means, sink gatingmeans coupling the bus means to inputs of the registers and to the mainmemorys and address means; wherein the main memory stores program wordsand data words, the program words having a format including operationcode bit positions and operand bit positions, means to read programwords into the instruction register, means to decode the operation codebit positions of the instruction register to supply operation codes tothe control means to execute an operation specified by the operationcode, which for some operation codes includes deriving an address fromthe operand bit positions of the instruction register to read or writedata words in the main memory; register memory control apparatus in theregister subsystem with means coupling the timing generator and commonlogic unit to the register memory, the output of the register memorybeinG coupled to the common logic unit; means coupling said bus meansvia address conductors to the register memory control apparatus, viaregister subsystem sink gating means and data conductors to the registermemory control apparatus, and means coupling said outputs of theregister memory via register subsystem source gating means to the busmeans; wherein said operation codes include a read register memoryinstruction and a write register memory instruction; means responsive toeither a read register memory or a write register memory instructiondecoded from the instruction register to gate an address derived fromthe operand to the register memory via the register memory controlapparatus to select the address in the register memory; means furtherresponsive to a read register memory instruction to supply a signal viathe register memory control apparatus to read from the register memory,and to gate data from the register memory output via the registersubsystem source gating means and the bus means to the accumulatorregister; and means further responsive to a write register memoryinstruction to supply a signal via the register memory control apparatusto write in the register memory, while gating data from the accumulatorregister via the bus means and the sink gating means to the registermemory, thereby providing the computer central processor with randomaccess to the register memory.
 2. In a communication switching system,the combination as claimed in claim 1, wherein there are a plurality ofregister-sender subsystems, and part of the effective address is used toselect one register-sender subsystem for supplying a read or writesignal thereto.
 3. In a communication switching system the combinationas claimed in claim 2, wherein each of said register-sender subsystemsand said stored program data processing unit are provided in duplicate,wherein from the computer central processor of each data processing unitsaid bus means and said signals responsive to read register memory andwrite register memory instructions are coupled to both of the duplicateunits of each registersender subsystem for selective use therein, andthe outputs of register memory of both of the duplicate units of eachregister-sender subsystem are coupled via register subsystem sourcegating means to the bus means in the computer central processor of eachdata processing unit, with means to selectively enable the last saidsource gating means.